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Ultra Fast FET-Input Operational Amplifier
LH0032 / LH0032C
FEATURES
CORPORATION
* 500V/s Slew Rate * 70MHz Bandwidth Impedance * 1012 Input2mV Max Input Offset Voltage * As Low as * FET Input Pot * Offset Null with SingleGains Above 50 * No Compensation for www..com * Peak Output Current to 100mA
GENERAL DESCRIPTION The LH0032 is a FET input, high slew rate amplifier capable of driving up to 100mA current. With wide bandwidth, high slew rate, high input impedance and high current drive capability, LH0032 is an ideal choice for many applications that includes high speed integrator, video amplifier, summing amplifier, high speed D/A converters, etc. ORDERING INFORMATION Part LH0032G LH0032CG Package H12A (TO8-12 Lead) H12A (TO8-12 Lead) Temperature Range -55oC to +125oC -25oC to +85oC
CONNECTION DIAGRAMS
OUTPUT COMPENSATION BALANCE/ COMPENSATION 3 4 INV INPUT 5 6 NON-INV INPUT NC NC Top View H12A 7 8 9 NC + 2 1 12 11 10 VOUT NC V+
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
LH0032 / LH0032C
CORPORATION
ABSOLUTE MAXIMUM RATINGS Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Input Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . 30V or 2VS Power Dissipation, PD TA = 25oC. . . . . . . . . . . . . 1.5W, derate 100oC/W to 125oC TC = 25oC. . . . . . . . . . . . . 2.2W, derate 70oC/W to 125oC Operating Temperature Range, TA LH0032G . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC LH0032CG . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to +85oC Operating Junction Temperature, TJ . . . . . . . . . . . . . . 175oC Storage Temperature Range . . . . . . . . . . . . -65oC to +150oC Lead Temp. (Soldering, 10 seconds). . . . . . . . . . . . . . 300oC
DC ELECTRICAL CHARACTERISTICS VS = 15V, TMIN TA TMAX unless otherwise noted (Note 1) (TA = T j)
LH0032 SYMBOL PARAMETER MIN
OS www..com
LH0032C UNITS TEST CONDITIONS MAX 5 10 50 25 250 25 100 1 50 MIN TYP 2 MAX 15 20 50 50 500 5 500 5 15 10 50 60 57 12 60 70 mV V/ o C pA pA nA pA nA nA V dB dB Note 6 VIN = 10V VO = 10V, f = 1kHz RL = 1k (Note 7) RL = 1k TA = 25oC, IO = 0 (Note 3) VS = 10V (5 to 15V) TJ = 25oC VIN = 0 TA = TJ = 25oC (Note 3) (Note 4) TJ = 25oC (Note 2) TA = 25oC (Note 3) TJ = 25oC (Note 2) TA = 25oC (Note 3)
TYP 2
V
Input Offset Voltage Average Offset Voltage Drift
VOS/T
15
15
IOS
Input Offset Current
IB
Input Bias Current 10 50 60 12 60 70
VINCM CMRR
Input Voltage Range Common Mode Rejection Ratio
AVOL
Open-Loop Voltage Gain 57
VO IS
Output Voltage Swing Power Supply Current Power Supply Rejection Ratio
10
13.5 18 20
10
13 20 22
V mA
PSRR
50
60
50
60
dB
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
LH0032 / LH0032C
CORPORATION
AC ELECTRICAL CHARACTERISTICS VS = 15V, RL = 1k, TJ = 25oC (Note 5)
SYMBOL SR ts ts tR tD Slew Rate Settling Time to 1% of Final Value Settling Time to 0.1% of Final Value Small Signal Rise Time Small Signal Delay Time PARAMETER MIN 350 TYP 500 100 AV = -1 300 8 10 20 25 ns AV = +1, VIN = 1V MAX UNITS V/s CONDITIONS AV = +1 VIN = 20V
Note 1. LH0032G/CG are 100% production tested as specified at 25 oC, Specifications at temperature extremes are verified by testing, periodic characterization, or correlation. Note 2. Specification is at 25oC junction temperature due to requirements of high-speed automatic testing. Actual values at operating temperature will exceed the value at TJ = 25oC. When supply voltages are 15V, no-load operating junction temperature may rise 40-60oC above www..comunder load conditions. Accordingly, VOS may change one to several mV, and IB and IOS will change significantly during ambient, and more warm-up. Refer to IB and I OS vs. temperature graph for expected values. Note 3. Measured in still air 7 minutes after application of power. Guaranteed thru correlated automatic pulse testing. Note 4. VOS/T is the average value calculated from measurements at 25 oC and TMAX, specifications at temperature are verified by testing, periodic characterization, or correlation. Note 5. Not 100% production tested; verified by testing, periodic characterization, or correlation. Note 6. Guaranteed by CMRR test condition. Note 7. Guaranteed thru correlated pulse testing at T j = 25 oC.
AUXILIARY CIRCUITS Offset Null
V+
Output Short Circuit Protection
V+ 12 6 LM113 2 LH0032 11
10k 12 6 INPUTS 5 4 + LH0032 10 V3 11 OUTPUT
+
62
5
-
10
V-
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
LH0032 / LH0032C
CORPORATION
TYPICAL PERFORMANCE CHARACTERISTICS
MAXIMUM POWER DISSIPATION
2.5
POWER DISSIPATION (W)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
24 22 TA = -55C
INFINITE HEAT SINK
SUPPLY CURRENT (mA)
2.0 JC = 70C/W 1.5
20 18 16 14 12 10 TA = +125C TC = 25C
1.0 NO HEAT SINK JA = 100C/W
0.5
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0
0
25
50
75
100
125
150
5
10
15
20
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
INPUT VOLTAGE RANGE AND OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
20 RL = 1k TC = 25C
VOLTAGE GAIN (dB) VINCM , VOUT (V)
BODE PLOT (UNCOMPENSATED)
80 VS = 15V 0 60 PHASE 40 45 90 135 180 GAIN 20 225 270
PHASE (DEGREES)
15 VOUT 10 VIN 5
0 0 5 10 15 20 SUPPLY VOLTAGE (V)
0 10k
100k
1M
10M
100M
FREQUENCY (Hz)
BODE PLOT (UNITY GAIN COMPENSATED)
80 VS = 15V
VOLTAGE GAIN (dB)
LARGE SIGNAL FREQUENCY RESPONSE
26 24 22 20 18 16 14 12 10 8 VS = 15V RL = 1k TC = +25C A V = +1
PHASE (DEGREES)
A V = +10
VOLTAGE GAIN (dB)
60 PHASE 40 GAIN 20 135 0 45 90
0 10k
100k
1M
10M
100M
6 10
100
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
LH0032 / LH0032C
CORPORATION
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
COMMON-MODE REJECTION RATIO (dB)
COMMON MODE REJECTION RATIO vs. FREQUENCY
90 80 70 60 50 40 30 20 VS = 15V RL = 1k
OUTPUT VOLTAGE (V)
LARGE SIGNAL PULSE RESPONSE
+10 VS = 15V A V = +1 RL = 1k
+5
0
-5
10 www..com 0 10k 100k 1M 10M 100M
-10 0 100 200 300 400 500
FREQUENCY (Hz)
TIME (ns)
LARGE SIGNAL PULSE RESPONSE
10
OUTPUT VOLTAGE (V)
NORMALIZED INPUT BIAS AND OFFSET CURRENT vs. JUNCTION TEMPERATURE
10 4
CURRENT - NORMALIZED TO CURRENT AT TJ = 25C
5
VS = 15V A V = +10 RL = 1k
10 3
0
10 2
-5
101
-10 0 100 200 300 400 500 10 0 25 45 65 85 105 125 145 165
TIME (ns)
JUNCTION TEMPERATURE (C)
NORMALIZED INPUT BIAS CURRENT DURING WARM-UP
100
CURRENT - NORMALIZED TO CURRENT AT TIME = 0
VS = 15V TA = 25C
10
1 0 2 4 6 8 10 TIME FROM POWER TURN-ON (MINUTES)
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
LH0032 / LH0032C
CORPORATION
TYPICAL APPLICATIONS Unity Gain Amplifier
8pF - 10pF V12 2k INPUT 6 + 2 3 LH0032 5 10 V4 100pF 11 OUTPUT
5 LH0032 10 INPUT 6 + V12 2 3 11 OUTPUT
10X Buffer Amplifier
5pF
9k
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100
1k
V-
100X Buffer Amplifier
V+
Non-Compensated Unity Gain Inverter
V+ 10k
INPUT
6
+
12 LH0032 11
+
5
-
10 V10k
10k INPUT 270
5
-
12 LH0032 11 OUTPUT
6 0.01
+
10 V+
100
High Speed Sample and Hold
100
V+ 2N2222 LH0032 + 10k VOUT
2N4391
VIN
100
2N3907
V-
CS = 1000pF
V+
1k
1N914
LOGIC CONTROL
1/2 DH0034
*Use polystyrene dielectric for minimum drift
V-
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
LH0032 / LH0032C
CORPORATION
TYPICAL APPLICATIONS (Continued) High Speed Current Mode MUX
3.8pF 4 R5
5
6
V12 R1 A1 2 AM9710 G1 3 1 G2 5 7 G3 10 8 G4 12 14 6 + 10 V11 5 LH0032
18F
2
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5.1k
3 11 VOUT
R2 A2 5.1k
6
R3 A3 5.1k
9
R4 A4 5.1k
13
APPLICATION INFORMATION: Power Supply Decoupling The LH0032, like most high speed circuits, is sensitive to layout and stray capacitance. Power supplies should be bypassed as near to pins 10 and 12 as practicable with low inductance capacitors such as 0.01F disc ceramics. Compensation components should also be located close to the appropriate pins to minimize stray reactances. Input Current Because the input devices are FETs, the input bias current may be expected to double for each 11oC junction temperature rise. This characteristic is plotted in the typical performance characteristics graphs. The device will self-heat due to internal power dissipation after application of power thus raising the FET junction temperature 40-60oC above free-air ambient temperature when supplies are 15V. The device temperature will stabilize within 5-10 minutes after application of power, and the input bias currents measured at that time will be indicative of normal operating currents. An additional rise would occur as power is delivered to a load due to additional internal power dissipation. There is an additional effect on input bias current as the input voltage is changed. The effect, common to all FETs, is an avalanche-like increase in gate current as the FET gate-to-drain voltage is increased above a critical value depending on FET geometry and doping levels. This effect will be noted as the input voltage of the LH0032 is taken below ground potential when the supplies are 15V. All of the effects described here may be minimized by operating the device with VS 15V. These effects are indicated in the typical performance curves. Input Capacitance The input capacitance to the LH0032/LH0032C is typically 5pF and thus may form a significant time constant with high value resistors. For optimum performance, the input
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
LH0032 / LH0032C
CORPORATION
capacitance to the inverting input should be compensated by a small capacitor across the feedback resistor. The value is strongly dependent on layout and closed loop gain, but will typically be in the neighborhood of several picofarads. In the non-inverting configuration, it may be advantageous to bootstrap the case and/or a guard conductor to the inverting input. This serves both to divert leakage currents away from the non-inverting input and to reduce the effective input capacitance. A unity gain follower so treated will have an input capacitance under a picofarad. Figure 1. LH0032 Frequency Compensation Circuit
Compensation Two compensation schemes may be used, depending on the designer's specific needs. The first technique is shown in Figure 1. It offers the best 0.1% settling time for a 10V square wave input. The compensation capacitors CC and CA should be selected from Figure 2 for various closed-loop gains. Figure 3 shows how the LH0032 frequency response is modified for different value compensation capacitors.
Figure 2. Recommended Value of Compensation Capacitor vs Closed-Loop Gain for Optimum Settling Time
COMPENSATION CAPACITANCE CC (pF) COMPENSATION CAPACITANCE CA (pF)
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R3
+15V 0.01F
10
100
R2
12 5_
LH0032
CA 4 11
3 2 OUTPUT
75
INPUT
R1
6+ 10
5 CA
CC
50
CC
25
0.01F -15V
0 1 10 100 CLOSED LOOP GAIN
0 1000
Figure 3. The Effect of Various Compensation Capacitors on LH0032 Open Loop Frequency Response
80
Figure 4. LH0032 Unity Gain Non-Inverting Large Signal Pulse Response: TA = 25oC, CC = 10pF, CA = 100pF
A VOL
VOLTAGE GAIN (dB)
60
40
C C = 0pF C C = 1pF 0 C C = 5pF C C = 10pF -45
10V
PHASE SHIFT (DEGREES)
20 C C = 5pF C C = 10pF 0 VS = 15V RL = 1k TA = 25C -20 10k 100k
-90 PHASE C C = 1pF C C = 0pF 1M 10M -135
-180 100M
10V
100nS
FREQUENCY (Hz)
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
LH0032 / LH0032C
CORPORATION
Although this approach offers the shortest settling time, the falling edge exhibits overshoot up to 30% lasting 200 to 300ns. Figure 4 shows the typical pulse response. If obtaining minimum ringing at the falling edge is the primary objective, a slight modification to the above is recommended. It is based on the same circuit as that of Figure 1. The values of the unity gain compensation capacitors CC and CA should be modified to 5pF and 1000pF, respectively. Figure 5 shows the suitable capacitance to use for various closed-loop gains. The resulting unity gain pulse response Figure 5. Recommended Value of Compensation Capacitor vs Closed-Loop Gain for Optimum Slew Rate
COMPENSATION CAPACITANCE CC (pF)
waveform is shown in Figure 6. The settling time to 1% final value is actually superior to the first method of compensation. However, the LH0032 suffers slow settling thereafter to 0.1% accuracy at the falling edge, and nearly four times as much at the rising edge, compared to the previous scheme. Note, however, that the falling edge ringing is considerably reduced. Furthermore, the slew rate is consistently superior using this compensation because of the smaller value of Miller capacitance CC required. The second compensation scheme works well with both inverting or non-inverting modes. Figure 7 shows the circuit schematic, in which a 270ohm resistor and a 0.01F capacitor are shunted across the inputs of the device. This lag compensation introduces a zero in the loop modifying the response such that adequate phase margin is preserved at unity gain crossover frequency. Note that the circuit requires no additional compensation. Heat Sinking While the LH0032 is specified for operation without any explicit heat sink, internal power dissipation does cause a significant temperature rise. Improved bias current performance can thus be obtained by limiting this temperature rise with a small heat sink such as the Thermalloy No. 2241 or equivalent. The case of the device has no internal connection, so it may be electrically connected to the sink if this is advantageous. However, that this will affect the stray capacitance to all pins and may thus require adjustment of circuit compensation values.
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4 1000
COMPENSATION CAPACITANCE CA (pF)
3 CC CA 1
2
500
0 1 10 100 CLOSED LOOP GAIN
0 1000
Figure 6. LH0032 Unity Gain Non-Inverting Large Signal Pulse Response: CC = 5pF, CA = 1000pF
Figure 7. LH0032 Non-Compensated Unity Gain Compensation
10V
+15V 1k 0.01F
1k
5_
270
12
LH0032
INPUT
11
OUTPUT
1k 0.01F
6+ 10
0.01F
10V
50nS
-15V
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076

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